New oscilloscope

If you follow both of our blogs, you may know that Kevin has recently organized a home lab and added some new equipment. I've been working on mine as well and I made a different decision regarding oscilloscopes: The Rigol DS1074Z.

I wanted a newer scope with deep memory and advanced trigger modes. I was especially interested in a scope with an Ethernet interface compatible with the VXI-11 standard. I'm hoping to use Python to unify my simulation and testing environments and this scope should help. I've already found an interesting python project, python-vxi11 and used it to communicate with the scope (see Figure 1).

I've also posted a gratuitous picture of my home office/lab to compete with Kevin (Figure 2).

Figure 1. Identify Query and Response from My DS1074Z.

Figure 2. The Scene of the Crime (see And the sparks fly...)

PCIe enumeration

Today was a day for good news and even better news. I passed the Titan PCBs to Kevin to review our options to get the board up and running, and I focused on the firmware any why the PCIe interface didn't enumerate on the Titan prototype.

Since the titan_wiggle project was a fork from ecp5dev_wiggle, I decided to validate that the Lattice ECP5 PCI Express Card enumerated properly on my test PC; It did not enumerate. I know that ecp5dev_wiggle enumerated in the past, but now I'm wondering if I failed to check PCIe enumeration at every step during development. The last two significant changes were the Diamond update from 3.2 to 3.3 and the pairing down of the project I did before I posted it to Github.

I followed IPUG112_01.2 closely and rebuilt the PCIe core in the Lattice Clarity tool in Diamond 3.3 and the PCIe interface still did not enumerate on the ECP5 dev card. I then rebuilt the project in Diamond 3.2 and the board enumerated properly. That explains why Titan didn't enumerate since it was running a direct fork of ecp5dev_wiggle in Diamond 3.3. I'm going to contact Lattice and see what might be wrong with my 3.3 project, but for now I can test Titan in Diamond 3.2 as soon as we have another working Titan.

On the PCB front, Kevin has been working working on an idea that we have to repair our Titan prototype. When I was last inspecting our rev A prototype the ECP5 popped of the board. Popping off wasn't that surprising since the rev A's pads were so small that we had virtually no ball collapse. Kevin's review of the part showed that we should be able to use it to replace the (possibly) damaged ECP5 on our rev B board. His next step is to isolate the LDOs on shorted rails from the ECP5 to determine if the failure is in the ECP5, the LDOs, or both.

And the sparks fly...

I'm still trying to wrap my head around it, but unfortunately I destroyed our only working Titan prototype while testing it. The build went very well, and I got a lot of good data from testing the card. While Kevin and I consider our next steps, I'll review how we got here.

Building

The rev B board assembly went very smoothly. I simplified the build by not loading the USB programming circuit, and I was able to place and reflow the board myself (including the two BGA parts). The only items that required manual rework after the build were two twisted capacitors and the switching power supply IC in a QFN package at U10. U10 also skewed in the same direction on the rev A build so we are going to examine this issue more deeply later.

Figure 1. U10, Skewed by a Pad.

We decided to simple remove U10 and bypass the 12V to 3.3V power supply and use the PCI Express connector's 3.3V rail instead. With U10 removed, this just required a simple mod-wire.

Testing

Prior to powering the board I measured the impedance to ground on each voltage rail:

Rail	Location Measured	Impedance
3.3V	C86	6 kOhms
2.5V_A	C60	4.8 kOhms
1.1V_A	C31	4.3 kOhms
1.1V	C59	79 Ohms
2.5V	C67	4.1 kOhms
1.5V	C27	2 kOhms

     Table 1. Impedance Measurements.

Rail	Location Measured	Voltage
3.3V	C86	3.472 V
2.5V_A	C60	2.49 V
1.1V_A	C31	1.099 V
1.1V	C59	1.096 V
2.5V	C67	2.480 V
1.5V	C27	1.499 V

     Table 2. Voltage Measurements.

Using a Lattice USB programmer, I used Diamond to validate that the ECP5 was identified with a JTAG scan. I then loaded my titan-wiggle test project and two LED expansion boards to validate That 64 I/O pins (32 to each expansion header) all work as my video shows.

Next I rebooted the Linux PC that was powering Titan and used the lspci command see if the PCI Express interface enumerated; It did not enumerate. I was able to validate the PERSTn (the PCI Express reset signal) and REFCLK were being received by the FPGA. Titan-wiggle uses PERSTn as its reset; I simply issued a warm reboot (linux reboot command) and saw that the LED counter reset during the PC's reboot. I then changed the LED counter from the 50MHz oscillator to the 125MHz output from the PCIe core and the LED counting pattern speed increased as I expected.

This is when the damage to Titan occurred. The mod-wire bypassing U10 was connected to a 3.3V via very close to the PCIe connector. With Titan installed into the PC and powered I accidentally nudged the board and the mod-wire popped off the via. The wire was under tension and swung across the card, most likely contacting the 12V rail on nearby caps. This would have shorted the ECP5's 3.3V rail directly to 12V. I saw a spark and a little smoke. As we all know, it is nearly impossible to return all of the smoke to an IC once it escapes :p  I powered off the unit and checked the voltage rails and found that the 3.3V, 2.5V, and 1.1V rails were all shorted to ground.

While this is disheartening, mistakes do happen, and hopefully we can recover quickly. For now I will be focusing on firmware development using the Lattice PCIe Development Kit and developing theories about why the PCI Express interface did not enumerate

More signs of life

I used two Dione LED boards and the titan_wiggle FPGA project to validate that all of the expansion I/O pins work. Next step, PCIe!

Titan Lives!

All of the power rails on the rev B board come up correctly and the FPGA is detected in Diamond via JTAG!

More details tonight.

Rev B, assembled

Figure 1. Titan Rev B, Assembled.

I just finished assembling a rev B board. I decided to leave of the on-board USB programmer for now to simplify the build. I'll use an external USB programmer to program the ECP5 if the board checks out.

Rev B arrives

Figure 1. Titan, Now with Bigger Pads!

Figure 2. BGA Pad Size Comparison (Left: Rev A, Right: Rev B).

Rev B arrived today. If all goes well I'll assemble a board tonight!

Another picture of rev B

Two more pictures from PCB-Pool just arrived. These show the surface finish of the PCBs being built:

Figure 1. Titan rev B Top Side (Surface Finish).

Figure 2. Titan rev B Bottom Side (Surface Finish).

Titan rev B Moves Along

Rev B of Titan is moving along nicely at PCB-Pool. I just received these plots:

Figure 1. Titan rev B Top Side.

Figure 2. Titan rev B Bottom Side.

Test setup

I've been giving some thought to the best development platform for Titan. I'm trying to optimize several criteria at the same time:

• Low cost
• While this seems self-evident, I'm not purely interested in cheap. I could always find a cheap PC with a PCI Express (PCIe) slot and use it. I'm looking for an inexpensive platform that also meets my other needs:
• Repeatability
• I'd like to find a platform that I can replicate in a hurry. The idea here is for Kevin and I to have similar setups that can be built up quickly and that we can share easily.
• Accessibility
• Accessibility is all about sharing. If I can create a common test platform that Kevin and I are both familiar with we will end up spending less time configuring test systems and more time developing HDL and hardware.
• Future Development Modeling
• I'm also interested in using test platforms that may model future FPGA/CPU pairings that show promise. This leads me to consider non-Intel platforms.
• Easy to Use with Linux

Usually I end up using one PC with my UUT (PCIe express card that I'm testing) and another PC with the JTAG programmer and other GUI based development tools. 

For Titan I'm considering moving to an environment where a small, low-cost platform is used to provide the PCIe link to Titan as well as the USB ports for any development tools that I need (JTAG programmer, logic analyzer, etc.). The plan is to use the USB/IP open source project to share the USB ports from the PCIe host platform to a my laptop (or Kevin's) where I can run the GUI based Lattice Diamond or SaleAE logic analyzer software. Figure 1 shows this idea.

Figure 1. Titan Development Configuration Idea.

I'll have to do some testing with USB/IP to see how practical this is, but I'm confident enough that I went ahead and ordered some hardware:

• SolidRun HummingBoard-i2eX
• $119.00 with AC power supply and 8GB micro-SD card.
• Bplus PM2 PCI-E / Mini PCI-E adapter
• $40. This is a little pricey and seems like a negative at first. I looked for a simple ARM-based processor board few low-cost options had PCIe slots (most had mini-PCIe like the Hummingboard). My long term plan is to build my own mini-PCIe to PCIe adapter with a GPIO input capable of power cycling Titan.

Making adjustments

Figure 1. Rev A of Titan, Assembled.

I posted a summary of our build experience with our first rev of Titan on the CES blog yesterday: Building Titan.

We completed the rev B updates to the artwork, released it on GitHub, and ordered new PCBs today. The changes are listed in the release notes on GitHub.