It's all about the paste

I finished building the last few BGA test boards today and learned a bit.  Here's an overview of my results including all six cards per component:

Part Type	Total Qty	Qty Failed	Yield
0805	18	0	100%
0603	12	0	100%
0605 (LED)	48	2	95.8%
0402	24	0	100%
QFN (0.65mm pitch)	6	0	100%
BGA (0.5mm pitch)	6	1	83.3%

I was able to correct the LED soldering issues by hand; I think that the parts were a little misaligned when I placed them.  The BGA issue looks like a short.  I'll do some more testing to try to confirm that.

Fortunately I was able to improve my assembly process and the last three boards built were trouble-free.  The most important improvement that I made while building the last three cards was to secure the stencil on only one side so that I could remove it quickly and avoid smearing the paste:

This method allowed for a very clean application of paste:

Better assembly led to prettier pictures:

Who afraid of 0.5mm?

Success! I was able to solder a 0.5mm pitch BGA on my bityBGA board tonight and only had to reflow a single joint by hand. I thought that a step-by-step guide would be interesting, but before I get into that a little background on bityBGA might be helpful. I designed the board to give me quick pass or fail feedback about whether the BGA CPLD was soldered correctly. I connected each CPLD I/O pin to a another non-adjacent I/O pin and then to the anode of a one color of a bi-color LED and the cathode of the other color:

This arrangement allows me to alternatively light either the red or green half of the bi-color LED.  To light the green LED I tri-state the red I/O pins, then drive the green anode high and the green cathode low.  Since adjacent pins are always either driven high or low I can identify BGA shorts.

While preparing to solder I ran quite a few temperature profiles.  I used Altera's SMT Board Assembly Process Recommendations (AN-353-4.0) to design my profile.  The target was to pre-heat at between 150 and 200 degrees Celsius for 60-120 seconds then heat between the eutectic and the CPLD's maximum temperature for another 60-120 seconds.  I profiled to PCB using some thermocouples, a Meterman meter with an RS232 interface, and a simple python script that I wrote to plot the temperature data against my profile in real time:

The green line in the plot above is the temperature on the PCB where the CPLD will be installed.  The yellow line is the temperature on the PCB at the component farthest away from the CPLD.  With a verified profile, the next step was to align the stencil:

Apply the paste:

Carefully remove the stencil:

Place the components:

Place some thermocouples to monitor the heating:

Heat the board:

Test it:

Next I'll build a few more to see how repeatable my process is.

Stencils

I ordered a low-cost mylar stencil form Pololu.  The total cost for a 2 square inch stencil was $31.95 (including shipping).  They charge $25 for the first 4 square inches and $1 per additional square inch.

After placing the Pololu order I found another stencil house with better pricing: OHARARP.   My total cost with OHARARP was $30.60 (including shipping) for six different stencils that fit on an 8.5" x 11" kapton sheet.  You can send up to six paste layers from different designs and OHARARP will automatically panelize them and separate the stencils before shipping.

For reference I've included a few pictures of the stencils below.  The OHARARP kapton stencils have much cleaner edges:

Pololu Stencil

OHARARP Stencil

Closer view of the stencils.  The OHARARP stencil is on the left.

New toys

I received my bityBGA boards today.  I'll use these boards to practice installing parts using solder paste and my IR reflow station.  If all goes well I'll post a video of the reflow process.

Strange bedfellows

How do you get ready to solder an Altera BGA?... with a Xilinx BGA, of course

I intend to build the rev B bityExpress prototype entirely on my own this time including the 484 pin BGA (Altera FPGA).  Since the part is so expensive I decided to practice on a simpler card with a cheaper BGA.  The result was a small, 2 layer PCB:

Layer 1 check-plot of bityBGA

I was hoping to use an Altera Max V CPLD like I used on the JTAG programmer, but the only BGA package available at Digikey was $12.00.  I found a 56pin BGA Xilinx Coolrunner-II for $1.60.  I should get the test board in about two weeks before the bityExpress rev B PCB.

Back on track

I ordered rev B of my simple Cyclone V PCIe card today.  I spent quite a bit of time trying to understand why the PCIe interface wouldn't function and I couldn't come to a definitive conclusion.  The misconnection of PERSTn (PCIe reset) seems like the best candidate.  I used the Altera BFM (bus functional model) to verify that my firmware works in simulation, but misconnecting PERSTn in the simulation did not cause the simulation to fail.

I decided to go ahead and roll another rev to address the issues that I'm aware of and we'll see how it goes.  My list of candidate problems (corrected on rev B) is below.  If rev B works I may modify a working card to reintroduce as many of the rev A errors as possible to see what the culprit was:

• PERSTn was connected to a general purpose I/O rather than nPERSTL1
• GXB_RX_L0 (PCIe data receive) and REFCLK0L (PCIe reference clock input) each had their polarity reversed on rev A.  The PCIe spec requires devices to support polarity inversion to simplify routing but I cannot find any clear documentation from Altera confirming that they comply with the spec.
• The unused reference clock inputs (REFCLK1L and REFCLK2L) were left floating and not tied to ground as the Altera documentation requires.
• VCCBAT was tied to 3.3V rather than something in the 1.2V to 3.0V range that Altera requires.

Layer 1 check-plot from OSH Park

Lobotomy, what Lobotomy?

On a whim I decided to boot up the FPGA after I drilled thru it:

I guess I missed the die.  Since I can't trust this part anymore I'll still need to replace it.  This will be my first chance to use my IR rework station on something I care about.

You win some...

It's amazing how quickly things go from almost there to way too far:

Drill, Baby, Drill

I've been working on an off lately trying to get the Cyclone V PCIe interface to come up.  Altera has some good documentation (ug_c5_pcie) that describes how to build a Qsys system for PCIe, but I've yet to see the interface enumerate on a Linux system.  Two problems seem to dominate the problem: I misconnected the PCI Express PERSTn (reset) pin and I'm not sure if the correct termination is being enabled on the PCIe differential pairs.

I connected the PCI Express PERSTn reset line to a general purpose I/O pin on the FPGA rather that the (correct) nPERSTL1 pin (pin R17 on my part).  Altera has a work around for the Stratix V and Arria V (rd04232012_285) but I can't get it to work on the Cyclone V.  The only way to completely eliminate this problem is to drill the PCB and add a mod-wire connection from R17 to the PERSTn net.

I emailed Altera about the termination issue.  Hopefully I'll hear back soon.

For now I've decided to go ahead and drill... might as well fix the problem I know about.  I practiced on a blank PCB:

Next stop:  The populated PCB...

Blinky

This is what every good EE loves the most.  The day he gets a blinky!

I implemented a simple counter in the FPGA and sent different bits of the counter to each edge connector I/O to verify that the BGA connection and PCB routing is correct.  I also sent a less-significant bit to a green LED and got my treat:

On-board JTAG controller lives!

This was a little frustrating.

My bityExpress PCB has a built-on programmer for the FPGA that includes a FTDI FT245R USB/FIFO IC and an Altera Max V CPLD.  I grabbed a copy of ixo.de's usb_jtag project for the CPLD and modified it to disable active serial mode and to match the pinout that I selected.  The code compiled cleanly for a 80 LE Max V.

The problem started when I tried to update the USB vendor ID on the FT245R to match the Altera USB-Blaster.  Installing FTDI's FT_Prog on my Windows 7 box never worked.  I ran across a Linux app called ftdi_eeprom that looked very promising.  I was able to change the vendor ID to 0x09FB and Quartus recognized the on-board programmer, but 'Auto Detect' in Quartus did not recognize the FPGA.  Two symptoms quickly emerged:  The JTAG TCK signal coming from the CPLD was constantly running and the FT245R's RXFn pin was stuck low (indicting that data was always in the FIFO).

Somehow the ftdi_eeprom app tells the FT245R that it is a FT232 and I could not find a way to recover the part.  Even when I successfully installed FT_Prog on an older XP box, I could not restore the original state of the FT245R.  I ended up replacing the FT245R and changing the vendor ID using FT_Prog on the XP system.  That's when the magic happened:



Perhaps I'll look deeper into ftdi_eeprom and try to understand why it fails on the FT245R.  I'd love to contribute something back.

Assembly almost complete

I loaded most of the remaining components today including all decoupling & bulk caps, the switching power supplies, and all four LDOs.

  Power-on tests proved that all voltage rails are correct.  After bypassing the USB/CPLD programming circuit I was able to detect the FPGA using Quartus via JTAG!  That means the board is working perfectly (so far).

Next I'm going to try to bring up the USB/CPLD programming logic.  Two interesting projects exist online: OpenJTAG and the ixo.de USB JTAG pod project.  ixo.de's usb_jtag project looks like the simplest path.  I will most likely start there and see if it works.  

BGA installed

The BGA is populated!

It looks like my friendly assembly house did a good job installing the Cyclone V FPGA.  I'm going to take a few impedance measurements next.  If they look good I'll start loading more components next week.

PCBs arrive

It's finally here!

Today I received a prototype PCB of a simple Altera Cyclone V GX PCIe design.  The edge connector on the right is based on Arrow's BeMicro designs.  I was able to build three PCBs for about 70 dollars at OSH Park. It was tough to meet OSH Park's 6mil trace width/spacing requirements on a 484 pin BGA but so far everything looks good.

I dropped a PCB and a single FPGA at a local assembly house to have it installed.  If all goes well I'll install the remaining parts over the next few days and start bringing the card up.