A new video about tools

I just posted my latest video on the CES blog. In this post I talk a bit about FPGA tool chains.

Memory woes

I've been getting up to speed on the Lattice Diamond development environment and targeting ECP3 FPGAs and I keep running across a cryptic "Done: error code 9" code when I try to synthesize my design.

Figure 1. Diamond error code reported during synthesis.

I searched around a bit and couldn't find a definition of the error code. I finally realized that the problem was related to memory usage on the PC running Diamond. I have Diamond installed on a lab PC and on a t1.micro instance in Amazon's cloud. The lab PC has been fine but the cloud instance gave the code 9 error intermittently during synthesis or mapping. I finally ran top on the command line and noticed just how low the instance's free memory was getting (less than 8MB).

I guess that I'll have to chalk this one up to me being too aggressive. I'll know better than to run Diamond on a t1.micro instance with 0.615 GB of RAM when Diamond requires 4GB for small ECP3s on a 64bit Linux box:

Figure 2. Linux memory requirements for Diamond 3.1 (from the Diamond Linux installation guide).

Say it ain't so, Lattice

It had to happen. I had my first disappointment with Lattice's Diamond FPGA tool. I've been working my way through their tutorial and I got stuck on Task 4: Verify Functionality with Simulation. When I tried to open the Aldec Active-HDL simulation tool it was no where to be found. After doing several Google searches and some time spent scouring the Lattice website, I found the culprit: The Linux version Diamond excludes Aldec.

The Linux version of Diamond ships without an HDL simulator... really?

It looks like Diamond supports ModelSim. I'll have to install it separately and see if I can connect them.

pyhwtest

A colleague recently posted his work using python to test PCI Express add-in cards on github (pyhwtest). This greatly simplifies testing since it doesn't require hardware engineers (like me) to write full fledged drivers. It is built for Linux but pyhwtest was originally developed for Windows. We may be able to get it running in Windows if anyone wants it.

My plan is to develop my own firmware project for the ECP3 Versa development card. When I tried to compile the standard Versa firmware using the latest Diamond tool I ran into quite a few errors. I'll take this as an excuse to rebuild the firmware and get use to using the Lattice tools and their interface cores. I'm hoping to squeeze in some myHDL experimentation while I'm at it.

Have you got a license for that?

I've been studying licenses for publishing my FPGA firmware and PCB designs (layout and schematics). FEDEVEL's imx6rex project is an interesting example. He uses the Creative Commons license. I'm note sure if it is appropriate, but I certainly like their license customization tools.

Versa

I received my new Lattice evaluation kit a few days ago:

It's cloudy out

After I decided to try Lattice's Diamond toolset, I had to find a place to install it. Recently I've been using Linux boxes to run the Xilinx and Altera toolsets and I've have very good success using the boxes remotely. This means either a graphical VNC connection or just SSH'ing into the box and running the FPGA tools from the command line.

Lattice presents an interesting opportunity. I've been running Ubuntu/Debian for quite a while and I'm comfortable with them. Unfortunately Lattice Diamond is built for RHEL (Red Hat Enterprise Linux) and I don't have a box set aside to install RHEL on. I've gone down the path of installing toolsets on unsupported Linux distributions; It usually works but it can be very time consuming.  My solution: Amazon EC2 (Amazon Elastic Compute Cloud).

I set up a AWS Free Usage Tier account a few months ago and this was the perfect excuse to start using it.  They had a free machine image that runs 64bit RHEL 6.4.  The free system's specs are pretty meager, but should be fast enough to see if this is worth pursuing.  I can always switch to a faster instance if I like it.

It took me a few hours to set the image up, learn how to enable a VNC session, and install Lattice Diamond.  If anyone is interested I'll consider writing up a tutorial.

Lattice

I've been reconsidering my FPGA selection lately. With my current interest in developing low-cost PCI Express designs, the $80 or so that I'm shelling out for each Altera Cyclone V GX is becoming a pricey way to work on my home-brew designs. Based on Digikey pricing, the cheapest Altera Cyclone V GX is ~$80, the cheapest Xilinx Spartan-6 25T is ~$50, and the Lattice ECP3 family capable of PCIe starts at around $30.

$30 is enough to entice me to test drive Lattice's development tools and see how mature they are.

And now for something completely different

You might be wondering why I decided to name this blog Co-simulation with synthesis.  I've been involved with PCB and FPGA design for most of my career.  At different times that has involved designs of varying complexity, but design verification is always critical.  I've also always had a strong interest in algorithm implementation.

The best development platform that I've ever worked with for algorithm development involved Matlab and Aldec.  We were able to develop signal processing algorithms in Matlab and co-simulate using Aldec (targeting Xilinx).  I was able to use SystemC to connect between Matlab and HDL simulations.  It allowed parallel development where I could load a dataset and process it with both the HDL simulation and the Matlab simulation and compare the results.  We could then automatically push the HDL simulation results back to Matlab and compare results.

I've wanted to replicate a development system like this for quite awhile but the tools are prohibitively expensive.  At the same time I've developed a strong appreciation for open source tools and the community that supports it.  I've identified tool projects that, when connected, might be able to meet or exceed the capabilities that I've been hoping to replicate: SciPy and MyHDL.

The final piece of the puzzle is verification in hardware.  When I realized that I could build interesting FPGA boards cost effectively I couldn't resist pushing ahead.  I should be able to directly compare results in simulation, simulated hardware, and real hardware.  Let the fun begin!