Say it ain't so, Lattice

It had to happen. I had my first disappointment with Lattice's Diamond FPGA tool. I've been working my way through their tutorial and I got stuck on Task 4: Verify Functionality with Simulation. When I tried to open the Aldec Active-HDL simulation tool it was no where to be found. After doing several Google searches and some time spent scouring the Lattice website, I found the culprit: The Linux version Diamond excludes Aldec.

The Linux version of Diamond ships without an HDL simulator... really?

It looks like Diamond supports ModelSim. I'll have to install it separately and see if I can connect them.

pyhwtest

A colleague recently posted his work using python to test PCI Express add-in cards on github (pyhwtest). This greatly simplifies testing since it doesn't require hardware engineers (like me) to write full fledged drivers. It is built for Linux but pyhwtest was originally developed for Windows. We may be able to get it running in Windows if anyone wants it.

My plan is to develop my own firmware project for the ECP3 Versa development card. When I tried to compile the standard Versa firmware using the latest Diamond tool I ran into quite a few errors. I'll take this as an excuse to rebuild the firmware and get use to using the Lattice tools and their interface cores. I'm hoping to squeeze in some myHDL experimentation while I'm at it.

First panel ordered

I ordered my first mini panel from PCB-Pool this morning!

PCB Panel Combining Several Prototypes.

Three little PCBs

I finished routing three boards tonight. As I'm moving from bityExpress to the new ECP5 design, I've identified some changes to the module form factor:

• The edge connector has been been moved from the base card to the module. This lets the modules be cheaper and simpler. This should make it easier for others to jump in and make new modules.
• I've moved from the Samtec MEC6 (0.635mm pitch) to the MEC8 (0.8mm pitch) connector. The larger pitch of the MEC8 makes the routing easier using larger geometries (cheaper PCBs!).
• The voltage rails are all on a single side of the connector to simplify routing.

Kevin and I are still debating the form factor, but I feel confident enough to order a few PCBs and test out this idea. The cards routed include:

A 0.1" header breakout board

An LED board (I *love* LED boards)

A CPLD (Lattice MACH 4000ZE) base card

The CPLD card will be useful to verify the connector pinout and it might be useful as a tester down the road. I'm going to try to panelize these boards myself. This will be my first order from PCB-Pool.

Have you got a license for that?

I've been studying licenses for publishing my FPGA firmware and PCB designs (layout and schematics). FEDEVEL's imx6rex project is an interesting example. He uses the Creative Commons license. I'm note sure if it is appropriate, but I certainly like their license customization tools.

Episode II is up!

Episode II of our web show is up:

Combat Engineering

A friend and I have just kicked off a new blog: customembeddedsolutions.blogpot.com. The development of my FPGA development card will be moving there. This will allow both of us to contribute to its development and give you an insight into how two engineers argue their way to a better design.

My CoSyn blog will focus a bit more on my original plan for it: Co-Simulation between algorithm, functional HDL, and hardware. I'll still use this as my personal development blog... so anything is possible!

Our first web video chronicling the new design is embedded below:

Another blog

A buddy of mine has just started a new blog at kevinkassner.wordpress.com. It looks like he is already pining for the latest and greatest from Tektronix.