Lobotomy, what Lobotomy?

On a whim I decided to boot up the FPGA after I drilled thru it:

I guess I missed the die.  Since I can't trust this part anymore I'll still need to replace it.  This will be my first chance to use my IR rework station on something I care about.

You win some...

It's amazing how quickly things go from almost there to way too far:

Drill, Baby, Drill

I've been working on an off lately trying to get the Cyclone V PCIe interface to come up.  Altera has some good documentation (ug_c5_pcie) that describes how to build a Qsys system for PCIe, but I've yet to see the interface enumerate on a Linux system.  Two problems seem to dominate the problem: I misconnected the PCI Express PERSTn (reset) pin and I'm not sure if the correct termination is being enabled on the PCIe differential pairs.

I connected the PCI Express PERSTn reset line to a general purpose I/O pin on the FPGA rather that the (correct) nPERSTL1 pin (pin R17 on my part).  Altera has a work around for the Stratix V and Arria V (rd04232012_285) but I can't get it to work on the Cyclone V.  The only way to completely eliminate this problem is to drill the PCB and add a mod-wire connection from R17 to the PERSTn net.

I emailed Altera about the termination issue.  Hopefully I'll hear back soon.

For now I've decided to go ahead and drill... might as well fix the problem I know about.  I practiced on a blank PCB:

Next stop:  The populated PCB...

Blinky

This is what every good EE loves the most.  The day he gets a blinky!

I implemented a simple counter in the FPGA and sent different bits of the counter to each edge connector I/O to verify that the BGA connection and PCB routing is correct.  I also sent a less-significant bit to a green LED and got my treat:

On-board JTAG controller lives!

This was a little frustrating.

My bityExpress PCB has a built-on programmer for the FPGA that includes a FTDI FT245R USB/FIFO IC and an Altera Max V CPLD.  I grabbed a copy of ixo.de's usb_jtag project for the CPLD and modified it to disable active serial mode and to match the pinout that I selected.  The code compiled cleanly for a 80 LE Max V.

The problem started when I tried to update the USB vendor ID on the FT245R to match the Altera USB-Blaster.  Installing FTDI's FT_Prog on my Windows 7 box never worked.  I ran across a Linux app called ftdi_eeprom that looked very promising.  I was able to change the vendor ID to 0x09FB and Quartus recognized the on-board programmer, but 'Auto Detect' in Quartus did not recognize the FPGA.  Two symptoms quickly emerged:  The JTAG TCK signal coming from the CPLD was constantly running and the FT245R's RXFn pin was stuck low (indicting that data was always in the FIFO).

Somehow the ftdi_eeprom app tells the FT245R that it is a FT232 and I could not find a way to recover the part.  Even when I successfully installed FT_Prog on an older XP box, I could not restore the original state of the FT245R.  I ended up replacing the FT245R and changing the vendor ID using FT_Prog on the XP system.  That's when the magic happened:



Perhaps I'll look deeper into ftdi_eeprom and try to understand why it fails on the FT245R.  I'd love to contribute something back.

Assembly almost complete

I loaded most of the remaining components today including all decoupling & bulk caps, the switching power supplies, and all four LDOs.

  Power-on tests proved that all voltage rails are correct.  After bypassing the USB/CPLD programming circuit I was able to detect the FPGA using Quartus via JTAG!  That means the board is working perfectly (so far).

Next I'm going to try to bring up the USB/CPLD programming logic.  Two interesting projects exist online: OpenJTAG and the ixo.de USB JTAG pod project.  ixo.de's usb_jtag project looks like the simplest path.  I will most likely start there and see if it works.  

BGA installed

The BGA is populated!

It looks like my friendly assembly house did a good job installing the Cyclone V FPGA.  I'm going to take a few impedance measurements next.  If they look good I'll start loading more components next week.