DDR3 data lines connected

I just finished routing both DDR3 data bytes from the memory IC (left side of Figure 1) to the FPGA (right side). Using 0.125mm traces (4.92mils) made the route easy. I only had to move a few of the address/control nets. The net reassignments were required because the Lattice ECP5 requires that all data bytes be routed to the same data group (named LDQ17, LDQ41, LDQ53, or LDQ89 on the left side of the ECP5).

Next I will tune the trace lengths of the address/control and data bytes. I'm going to start with a ruleset that was developed for a 1333 Mbps DDR3 design. Since the ECP5's maximum data rate is 800 Mbps this ruleset should be overkill. If the route becomes too difficult I'll reconsider the rules.

For now my goal is to get a route that is good enough so that I have something to simulate. Here's hoping that I'll have a simulation ready design soon.

Figure 1. Data Connection (2 Bytes) from DDR3 IC to FPGA.

The PCB layout shown in this post by Custom Embedded Solutions, LLC. is licensed under a Creative Commons Attribution 4.0 International License.