You might be wondering why I decided to name this blog

*Co-simulation with synthesis*. I've been involved with PCB and FPGA design for most of my career. At different times that has involved designs of varying complexity, but design verification is always critical. I've also always had a strong interest in algorithm implementation.

The best development platform that I've ever worked with for algorithm development involved Matlab and Aldec. We were able to develop signal processing algorithms in Matlab and co-simulate using Aldec (targeting Xilinx). I was able to use SystemC to connect between Matlab and HDL simulations. It allowed parallel development where I could load a dataset and process it with both the HDL simulation and the Matlab simulation and compare the results. We could then automatically push the HDL simulation results back to Matlab and compare results.

I've wanted to replicate a development system like this for quite awhile but the tools are prohibitively expensive. At the same time I've developed a strong appreciation for open source tools and the community that supports it. I've identified tool projects that, when connected, might be able to meet or exceed the capabilities that I've been hoping to replicate:

SciPy and

MyHDL.

The final piece of the puzzle is verification in hardware. When I realized that I could build interesting FPGA boards cost effectively I couldn't resist pushing ahead. I should be able to directly compare results in simulation, simulated hardware, and real hardware. Let the fun begin!