Saturday, February 22, 2014

bityExpress-C PCB inspection

I grabbed a few pictures of the three new bityExpress-C PCBs.  These boards were built with a 4 mil solder mask expansion.  Vias have an 10 mil drill with 5 mil annular rings.  This is more conservative than the 4 mil annular ring vias that I used on bityExpress-B.

The boards look good overall.  Board #3 has the worst solder mask alignment, but it is acceptable.  I'll need to measure it more closely, but based on my initial inspection it looks like I may have to stick with a solder mask expansion of 4 mils.  If I had used a 2 mil expansion this card may have had solder mask on the BGA pads.

The via drills look appropriately sized and well aligned.  On to assembly!

bityExpress-C sn #1 BGA solder mask alignment

bityExpress-C sn #2 BGA solder mask alignment

bityExpress-C sn #3 BGA solder mask alignment

bityExpress-C sn #1 QFN solder mask alignment

bityExpress-C sn #2 QFN solder mask alignment

bityExpress-C sn #3 QFN solder mask alignment

bityExpress-C sn #1 drill/annular ring

bityExpress-C sn #2 drill/annular ring

bityExpress-C sn #3 drill/annular ring

Friday, February 21, 2014

Rev C has arrived

It seemed like it took forever to get bityExpress-C in, but it was almost exactly one month.

Wednesday, February 19, 2014

Why can you sit still?

I was building some boards that were similar to bityExpress last week.  The boards had SMT components on both sides and the back-side build went perfectly.  When I ran the top sides (which included a similar FPGA), everything looked good until I inspected the cards closely.  The solder on all of the SMT components flowed well and everything centered up nicely except the FPGA BGA.  At first I assumed that I had placed the parts badly, but when I spoke with my friendly neighborhood failure analysis expert he zeroed in on a different cause:  a too-rapid cooling profile.

His theory is that if the BGA and PCB are allowed to cool at different rates, the stresses applied to the cooling solder can cause the part to twist before the solder solidifies.  Since my current profile involves opening the toaster oven door 90 seconds after all of the solder joints have flowed, I think that his theory is plausible.  I should have my bityExpress-C boards in this weekend so we'll see if I have better luck with the BGA soldering with a slower cooling profile.

Tuesday, February 4, 2014

And now for something completely different

You might be wondering why I decided to name this blog Co-simulation with synthesis.  I've been involved with PCB and FPGA design for most of my career.  At different times that has involved designs of varying complexity, but design verification is always critical.  I've also always had a strong interest in algorithm implementation.

The best development platform that I've ever worked with for algorithm development involved Matlab and Aldec.  We were able to develop signal processing algorithms in Matlab and co-simulate using Aldec (targeting Xilinx).  I was able to use SystemC to connect between Matlab and HDL simulations.  It allowed parallel development where I could load a dataset and process it with both the HDL simulation and the Matlab simulation and compare the results.  We could then automatically push the HDL simulation results back to Matlab and compare results.

I've wanted to replicate a development system like this for quite awhile but the tools are prohibitively expensive.  At the same time I've developed a strong appreciation for open source tools and the community that supports it.  I've identified tool projects that, when connected, might be able to meet or exceed the capabilities that I've been hoping to replicate: SciPy and MyHDL.

The final piece of the puzzle is verification in hardware.  When I realized that I could build interesting FPGA boards cost effectively I couldn't resist pushing ahead.  I should be able to directly compare results in simulation, simulated hardware, and real hardware.  Let the fun begin!

Monday, February 3, 2014

What's in a sliver?

When discussing my last post with a colleague, I realized that I explained why one would want to set a minimum solder mask, but not why one would need to set a maximum.

While the minimum is based on the PCB vendor's ability to properly register the solder mask when printing it, the maximum is all about the whether or not small-pitch components get solder mask between their pads or not.  In the screen captures below, the component on the right is the Altera MAX V package that has 0.4mm pitch pins.  With a 4 mil solder mask expansion there is no solder mask between the pins.  With a 2 mil expansion some mask is placed between the CPLD's pads.

4 mil solder expansion (bityExpress-B)

2 mil solder expansion
It is possible that the lack of solder mask between the CPLD's (U4's) pads is why I had a few solder bridges.