Panel Assembly

I just posted a new video where I assembled my first prototype panel from PCB-Pool. Check it out on the CES blog: http://customembeddedsolutions.blogspot.com/2014/06/in-todays-video-john-builds-small.html

Here's a picture of the logo (because I think it's cool):

A new video about tools

I just posted my latest video on the CES blog. In this post I talk a bit about FPGA tool chains.

PCB-Pool Panel

I received my first mini-panel from PCB-Pool today. At first glance it looks really good. The biggest surprise was that I got two stencils when I only expected one. There must be a mistake for the edge connector on the paste paste layer (they shouldn't be pasted), but that mistake means that I now know that you can get two stencils just by including the bottom paste layer!

Figure 1. Nice Box!

Figure 2. PCB Panel and Two Stencils!

Figure 3. Panel Close-Up

Tag-Connect

I got my test cable and clip from Tag-Connect today. I've been looking for something like this for quite a while. Tag-Connect cables require a very small footprint pad and no connector on a PCB. This is perfect for a test connection that is only used in development (like JTAG for an FPGA). I placed a footprint for the 6 pin TC2030-IDC-NL on the CPLD design that I expect to early next week. I used the NL (no legs) version to get as small a footprint as possible. This meant that I needed a special clip to hold the cable to my PCB (see Figure 2).

Figure1. 6 Pin Tag-Connect Cable, Clip, and Example PCB.

Figure 2. Tag-Connect Cable Held in Place on the PCB with a Clip.

Memory woes

I've been getting up to speed on the Lattice Diamond development environment and targeting ECP3 FPGAs and I keep running across a cryptic "Done: error code 9" code when I try to synthesize my design.

Figure 1. Diamond error code reported during synthesis.

I searched around a bit and couldn't find a definition of the error code. I finally realized that the problem was related to memory usage on the PC running Diamond. I have Diamond installed on a lab PC and on a t1.micro instance in Amazon's cloud. The lab PC has been fine but the cloud instance gave the code 9 error intermittently during synthesis or mapping. I finally ran top on the command line and noticed just how low the instance's free memory was getting (less than 8MB).

I guess that I'll have to chalk this one up to me being too aggressive. I'll know better than to run Diamond on a t1.micro instance with 0.615 GB of RAM when Diamond requires 4GB for small ECP3s on a 64bit Linux box:

Figure 2. Linux memory requirements for Diamond 3.1 (from the Diamond Linux installation guide).

Say it ain't so, Lattice

It had to happen. I had my first disappointment with Lattice's Diamond FPGA tool. I've been working my way through their tutorial and I got stuck on Task 4: Verify Functionality with Simulation. When I tried to open the Aldec Active-HDL simulation tool it was no where to be found. After doing several Google searches and some time spent scouring the Lattice website, I found the culprit: The Linux version Diamond excludes Aldec.

The Linux version of Diamond ships without an HDL simulator... really?

It looks like Diamond supports ModelSim. I'll have to install it separately and see if I can connect them.

pyhwtest

A colleague recently posted his work using python to test PCI Express add-in cards on github (pyhwtest). This greatly simplifies testing since it doesn't require hardware engineers (like me) to write full fledged drivers. It is built for Linux but pyhwtest was originally developed for Windows. We may be able to get it running in Windows if anyone wants it.

My plan is to develop my own firmware project for the ECP3 Versa development card. When I tried to compile the standard Versa firmware using the latest Diamond tool I ran into quite a few errors. I'll take this as an excuse to rebuild the firmware and get use to using the Lattice tools and their interface cores. I'm hoping to squeeze in some myHDL experimentation while I'm at it.