Friday, August 30, 2013

Assembly almost complete

I loaded most of the remaining components today including all decoupling & bulk caps, the switching power supplies, and all four LDOs.

  Power-on tests proved that all voltage rails are correct.  After bypassing the USB/CPLD programming circuit I was able to detect the FPGA using Quartus via JTAG!  That means the board is working perfectly (so far).

Next I'm going to try to bring up the USB/CPLD programming logic.  Two interesting projects exist online: OpenJTAG and the USB JTAG pod project.'s usb_jtag project looks like the simplest path.  I will most likely start there and see if it works.  

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