Drill, Baby, Drill

I've been working on an off lately trying to get the Cyclone V PCIe interface to come up.  Altera has some good documentation (ug_c5_pcie) that describes how to build a Qsys system for PCIe, but I've yet to see the interface enumerate on a Linux system.  Two problems seem to dominate the problem: I misconnected the PCI Express PERSTn (reset) pin and I'm not sure if the correct termination is being enabled on the PCIe differential pairs.

I connected the PCI Express PERSTn reset line to a general purpose I/O pin on the FPGA rather that the (correct) nPERSTL1 pin (pin R17 on my part).  Altera has a work around for the Stratix V and Arria V (rd04232012_285) but I can't get it to work on the Cyclone V.  The only way to completely eliminate this problem is to drill the PCB and add a mod-wire connection from R17 to the PERSTn net.

I emailed Altera about the termination issue.  Hopefully I'll hear back soon.

For now I've decided to go ahead and drill... might as well fix the problem I know about.  I practiced on a blank PCB:

Next stop:  The populated PCB...