Friday, December 19, 2014

Expansion interface

We are finalizing our plans for rev C of Titan now. Over the last week Kevin has been working on our current change list: layout adjustments to ease manufacture, tighter tuning of the expansion header traces, and the addition of a 1.2V power supply for the SerDes (PCIe) transmitter and receiver. Kevin is working in his fork of the Titan project. Once he completes his changes I'm going to make a few adjustments to the DDR3 layout. When we are ready to order we will pull the changes back into the master branch of Titan on the C-E-S organization Github page.

While Kevin is updating the layout, I've been focused on validated our changes. Initially I was working on using the Diamond's Reveal embedded logic analyzer to identify the PCIe issues. Now that I know that there isn't a PCIe core in the samples we have, I'm focusing my efforts on validating the DDR3 memory design and the external interfaces.

Figure 1. Titan Rev B with Two Expansion Modules Installed.

Our expansion headers bring out a single bank of the ECP5 FPGA to a single connector. Now that we've had more time to consider possible expansion modules it has become clearer how we should organize the connections from the FPGA's I/O banks to the connectors. We are trying to balance keeping the layout simple and clean with our desire to standardize the expansion header pinout to make our future modules interchangeable from one Titan header to another.

Each FPGA bank that we have connected to an expansion header can be configured as 32 single-ended GPIOs, 16 differential GPIOs, two DDR data groups, or 7:1 geared interfaces (ie. CameraLink). Lattice's ECP5 High-Speed I/O Interface guide describes the interface possibilities. One specific interface that we are studying that has applications with SDR is the Linear Technology LTC217x quad ADC.

This leads me to my list of features that need to be the same from one expansion header to another. These assignments are based on the expansion differential pair nomenclature used on the rev B Titan schematic (see Figure 2).

Figure 2. Titan Expansion Header (showing our simple nomenclature).

Titan Expansion Header Features

  • One PCLK pair must assigned to a fixed diff pair (ie. DO_P/N)
  • Each of the two DQS pairs must be assigned to a fixed diff pair (ie D8_P/N and D12_P/N)
    • Each DQ group must be matched to the same set of diff pairs (ie D0/1/2/3/9/10/11_P/N)
  • VREF must be assigned to a fixed net (ie. D1_P)
  • All LVDS transmit pairs must be connected to the same side of the expansion connector (ie. D0/1/2/3/4/5/6/7_P/N)
  • All trace lengths must be matched to within 20mils and may not exceed 2000mils.
Now we'll see if I've given Kevin an impossible set of requirements. If I have I'm sure that I'll hear about it.

2 comments:

Tim 'Mithro' Ansell said...

I haven't been able to figure out from the pictures what type of connectors you are using for the expansion? It looks like it uses PCB fingers on one side but not a PCI Express connector.

Have you considered using PCI Express connectors? We need an "open" standard for FPGA expansion boards which uses cheap connectors (available in small quantities). The FMC connectors are just way too expensive. For low speed stuff stuff, PMOD seems to be what people have settled on.

Are you interested in collaborating on trying to get such a standard off the ground? I've been collecting all the standard I/O layouts in a spreadsheet to try and figure out how to cover as many possibilities as possible. (PS You can contact me at mithro@mithis.com if you'd like to email.)

John Sloan said...

The connector is a MEC8-130 (60 pin connector) from Samtec: http://www.samtec.com/technical-specifications/Default.aspx?SeriesMaster=mec8-ra The exact part number is MEC8-130-02-L-D-RA1

We considered using PCIe connectors. We ended up going with the MEC8 for a few reasons: possible confusion with PCIe, larger pitch size than the MEC8, and mounting concerns (we wanted to go all single sided SMT and could't find a good PCIe option).

You're right that the module side has edge fingers. We got the idea from Altera's BeMicro design but we decided to put the edge fingers on the modules. This way the cost and hassle of finding the connectors is only an issue for the people making a base board (us). This seemed like a good idea since we expect most people will want to make their own modules rather than base boards.

Right now our focus is a little narrow and we are trying to find a good header for the ECP5. That said I love the idea of finding a more universal solution. I've been just as unhappy with the HSMC connector that seems to be popular. I'll contact you soon (or feel free to contact me at jsloan256@gmail.com)