Tuesday, January 6, 2015

Expansion interface: the re-route

Over the holiday I've been considering how painful it will be to re-route the expansions headers on Titan to meet (or approximate) the rules that I defined last week. The answer: Really, really, painful.

The current route is layer efficient and has very few layer transitions (both fantastic qualities). Unfortunately, this natural matching of an ECP5 bank to an expansion connector places DQ groups/strobes, PCLK inputs, and the VREF all over the place. Table 1 shows my analysis of the pinout comparison between expansion headers P3 and P5. I realize that this table is a little busy, but I was trying to look at several different factors at the same time. I considered posting the color version, but it is a rather terrifying to behold.

P5 FunctionP3 FunctionP3 FunctionP5 Function
DQPairOthDQPairOthTop Side NetPin #Bottom Side NetDQPairOthDQPairOth
89C41CPCLKD0_P (S0)87D8_P (S16)41A89A
89D41DPCLKD0_N (S1)109D8_N (S17)41B89B
89A41ADQSD1_P (S2)1413D9_P (S18)41C89C
89B41BDQSD1_N (S3)1615D9_N (S19)41D89D
89A17ADQSD2_P (S4)2019D10_P (S20)17A89ADQS
89B17BDQSD2_N (S5)2221D10_N (S21)17B89BDQS
53CPCLK41CD3_P (S6)2625D11_P (S22)17C89C
53DPCLK41DD3_N (S7)2827D11_P (S22)17D89D
53C41AD4_P (S8)3433D12_P (S24)17C53C
53D41BD4_N (S9)3635D12_N (S25)17D53D
53C17AD5_P (S10)4039D13_P (S26)17C89C
53D17BD5_N (S11)4241D13_N (S27)17D89D
53A41CVREFD6_P (S12)4645D14_P (S28)17A53A
53B41DD6_N (S13)4847D14_N (S29)17B53B
53ADQS41AD7_P (S14)5251D15_P (S30)17C53A
53BDQS41BD7_N (S15)5453D15_N (S31)17D53BVREF
Table 1. P3 & P5 Pin Mappings.

Figures 1 and 2 show the scale of the problem. Figure 2 especially shows just how clean the current route is. I spent quite awhile looking at different pinouts where where only the most critical nets were routed to the same connector pin. The scale of the change quickly becomes so severe that it doesn't look possible without adding quite a few layer transitions (bad for signal quality) and possibly using more PCB layers (bad for PCB cost).

Figure 1. The Spaghetti Monster.

Figure 2. Routing Layers for the Expansion Interface.

I only have one knob left to twist: function. I have a hunch that only routing about half of the nets as differential pairs will make it much easier to route the rest as single-ended nets. I have a few use-cases in mind. Hopefully I'll find a way to map them to a rational pin mapping.

Reading this you might wonder why I'm taking so much time with this re-planning of the expansion interface. The first is simple: I believe that an intelligent pin assignment will ease the design of modules. The second is all in the schedule: We have our first order of ECP5 FPGA's on the way, but the lead time is long enough for us to give a careful review of the entire design before placing our next PCB order. We intentionally side-stepped the tricky problem of the expansion header design in our first two PCB revs. Now that the rest of the design is stable (or nearly stable), it's time to reconsider this part of the design.

No comments: