Expansion interface: the re-route

Over the holiday I've been considering how painful it will be to re-route the expansions headers on Titan to meet (or approximate) the rules that I defined last week. The answer: Really, really, painful.

The current route is layer efficient and has very few layer transitions (both fantastic qualities). Unfortunately, this natural matching of an ECP5 bank to an expansion connector places DQ groups/strobes, PCLK inputs, and the VREF all over the place. Table 1 shows my analysis of the pinout comparison between expansion headers P3 and P5. I realize that this table is a little busy, but I was trying to look at several different factors at the same time. I considered posting the color version, but it is a rather terrifying to behold.

P5 Function			P3 Function							P3 Function			P5 Function
DQ	Pair	Oth	DQ	Pair	Oth	Top Side Net	Pin #		Bottom Side Net	DQ	Pair	Oth	DQ	Pair	Oth
						3.3V	2	1	V_I/O
						3.3V	4	3	V_I/O
						GND	6	5	GND
89	C		41	C	PCLK	D0_P (S0)	8	7	D8_P (S16)	41	A		89	A
89	D		41	D	PCLK	D0_N (S1)	10	9	D8_N (S17)	41	B		89	B
						GND	12	11	GND
89	A		41	A	DQS	D1_P (S2)	14	13	D9_P (S18)	41	C		89	C
89	B		41	B	DQS	D1_N (S3)	16	15	D9_N (S19)	41	D		89	D
						GND	18	17	GND
89	A		17	A	DQS	D2_P (S4)	20	19	D10_P (S20)	17	A		89	A	DQS
89	B		17	B	DQS	D2_N (S5)	22	21	D10_N (S21)	17	B		89	B	DQS
						GND	24	23	GND
53	C	PCLK	41	C		D3_P (S6)	26	25	D11_P (S22)	17	C		89	C
53	D	PCLK	41	D		D3_N (S7)	28	27	D11_P (S22)	17	D		89	D
						GND	30	29	GND
						GND	32	31	GND
53	C		41	A		D4_P (S8)	34	33	D12_P (S24)	17	C		53	C
53	D		41	B		D4_N (S9)	36	35	D12_N (S25)	17	D		53	D
						GND	38	37	GND
53	C		17	A		D5_P (S10)	40	39	D13_P (S26)	17	C		89	C
53	D		17	B		D5_N (S11)	42	41	D13_N (S27)	17	D		89	D
						GND	44	43	GND
53	A		41	C	VREF	D6_P (S12)	46	45	D14_P (S28)	17	A		53	A
53	B		41	D		D6_N (S13)	48	47	D14_N (S29)	17	B		53	B
						GND	50	49	GND
53	A	DQS	41	A		D7_P (S14)	52	51	D15_P (S30)	17	C		53	A
53	B	DQS	41	B		D7_N (S15)	54	53	D15_N (S31)	17	D		53	B	VREF
						GND	56	55	GND
						n/c	58	57	n/c
						n/c	60	59	n/c

Table 1. P3 & P5 Pin Mappings.

Figures 1 and 2 show the scale of the problem. Figure 2 especially shows just how clean the current route is. I spent quite awhile looking at different pinouts where where only the most critical nets were routed to the same connector pin. The scale of the change quickly becomes so severe that it doesn't look possible without adding quite a few layer transitions (bad for signal quality) and possibly using more PCB layers (bad for PCB cost).

Figure 1. The Spaghetti Monster.

Figure 2. Routing Layers for the Expansion Interface.

I only have one knob left to twist: function. I have a hunch that only routing about half of the nets as differential pairs will make it much easier to route the rest as single-ended nets. I have a few use-cases in mind. Hopefully I'll find a way to map them to a rational pin mapping.

Reading this you might wonder why I'm taking so much time with this re-planning of the expansion interface. The first is simple: I believe that an intelligent pin assignment will ease the design of modules. The second is all in the schedule: We have our first order of ECP5 FPGA's on the way, but the lead time is long enough for us to give a careful review of the entire design before placing our next PCB order. We intentionally side-stepped the tricky problem of the expansion header design in our first two PCB revs. Now that the rest of the design is stable (or nearly stable), it's time to reconsider this part of the design.