Co-simulation with synthesis

Wednesday, March 25, 2015

DDR3 re-check

I decided to double check the DDR3 routing before finishing rev C of Titan, and I found a few length tuning issues to correct. The updates are committed on github: https://github.com/jsloan256/titan/tree/Rev-C.


Figure 1. Superfluous Picture of Titan's Updated DDR3 Routing.

Posted by Unknown at 2:24 PM
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Labels: DDR3, ECP5, PCB Design, Titan

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