Back on track

I ordered rev B of my simple Cyclone V PCIe card today.  I spent quite a bit of time trying to understand why the PCIe interface wouldn't function and I couldn't come to a definitive conclusion.  The misconnection of PERSTn (PCIe reset) seems like the best candidate.  I used the Altera BFM (bus functional model) to verify that my firmware works in simulation, but misconnecting PERSTn in the simulation did not cause the simulation to fail.

I decided to go ahead and roll another rev to address the issues that I'm aware of and we'll see how it goes.  My list of candidate problems (corrected on rev B) is below.  If rev B works I may modify a working card to reintroduce as many of the rev A errors as possible to see what the culprit was:

• PERSTn was connected to a general purpose I/O rather than nPERSTL1
• GXB_RX_L0 (PCIe data receive) and REFCLK0L (PCIe reference clock input) each had their polarity reversed on rev A.  The PCIe spec requires devices to support polarity inversion to simplify routing but I cannot find any clear documentation from Altera confirming that they comply with the spec.
• The unused reference clock inputs (REFCLK1L and REFCLK2L) were left floating and not tied to ground as the Altera documentation requires.
• VCCBAT was tied to 3.3V rather than something in the 1.2V to 3.0V range that Altera requires.

Layer 1 check-plot from OSH Park