Sunday, March 9, 2014


I heard back from OSH Park about the shorts on bityExpress-C. My board meets their design rules and the shorts are a fab error. That said, they are recommending larger polygon to polygon (plane) spacing on internal layers (2 to 3 mils above the clearance spec). I'm concerned that they may not be specifying some rules that they should be; I've decided to look into rule sets from some other PCB prototype houses to look for common themes.

VendorTrack Width / GapSmallest DrillVia Annular RingComponent Annular RingBoard Edge to CopperDrill to Copper GapPlane to Plane ClearanceSolder Mask SilverSolder Mask Expansion
OSH Park5104 (5*)nsnsnsns (7-8*)nsns (4*)
ns = not specified, * = guess based on experience

PCB-Pool's rule listing is more complete than OSH Park's. Given how similar they are I'm inclined to generalize my prototyping rule set in Altium to work for both vendors.

PCB-Pool's Drill to Copper Gap caught my attention. This rule defines how far copper on an internal layer must be from a drill with a different net.  With the bityExpress-C ruleset, the 5 mil annular ring rule plus the 5 mil clearance rule meant that my PCB had a 10 mil Drill to Copper Gap where the PCB-Pool rule is 12 mils. This is especially interesting because if I increase my Plane to Plane Clearance (polygons in this case) to the 7 mils that OSH Park recommended, I also meet PCB-Pool's Drill to Copper Gap rule.

All of this makes me wonder if OSH Park was right that the bityExpress-C shorts are inter-plane shorts. It's possible that the shorts are really due to inaccurate drills hitting planes. I'll give this some more thought. Perhaps I can drill out the vias on one shorted net and see if I can clear the short.

OSH Park wanted to re-run the PCB so I updated it to rev C1. The only change made was to bump the polygon clearance rule to 7 mils. I'm already working on some plans for rev D (which will most likely be built at PCB-Pool). I'll post about my rev D plans soon.

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