I finished routing and tuning the DDR3 circuit last night. My branch of the Titan PCB layout is now in Kevin's hands for re-integration into trunk. I'll post some screen caps of the layout when the integration is complete. My next task will be to build a test project for the Lattice's new ECP5 PCI Express Board. When I get it working I'll port the code to Titan and validate our pinout.
Until then, enjoy our latest post at the CES blog: Lattice's ECP5 PCI Express Card
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