DDR3 data group tuning

I moved half of the upper byte to layer 4 and tuned the tracks. I was shooting to tune each byte to within 100mils, but I ended up beating that without really trying. The lower byte is tuned within 32 mils (see Table 1) and the upper byte is tuned within 21 mils (Table 2).

Figures 1 and 2 (below) show the routes on layers 4 and 6. All of the tracks in the data groups except for the DQS differential pairs are shown; They are routed on layers 1 and 3.

	Pre-tuned length (mils)	Post-tuned length (mils)
D0	859	1205
D1	855	1185
D2	839	1178
D3	934	1210
D4	1027	1204
D5	1187	1187
D6	934	1194
D7	1016	1202
DM0	802	1202
DQS0p	1200	1200
DQS0n	1194	1194

Table 1. Pre and Post Track Lengths for the Lower Byte.

	Pre-tuned length (mils)	Post-tuned length (mils)
D8	962	962
D9	861	981
D10	877	982
D11	975	972
D12	746	961
D13	868	978
D14	803	970
D15	953	973
DM0	888	974
DQS1p	983	983
DQS1n	924	973

Table 2. Pre and Post Track Lengths for the Upper Byte.

Figure 1. Tuned Data Tracks on Layer 6 (Upper Byte and Half of Lower Byte).

Figure 2. Tuned Data Tracks on Layer 4 (Half of Lower Byte).

The PCB layout shown in this post by Custom Embedded Solutions, LLC. is licensed under a Creative Commons Attribution 4.0 International License.