DDR3 Control Architectures

With Kevin working on the main Titan layout, I've been focusing on the DDR3 layout and building a simple FPGA project to validate our pin selection. I expect to post the FPGA project to my github account: https://github.com/jsloan256. Be warned, I'm still learning to use git and posting testing code; I don't guarantee that anything works. When I reach a milestone I'll post about it here and link to the github commit.

The DDR3 design on Titan will use a simple point to point topology. Unlike more traditional module DDR3 designs like one would find on a PC motherboard, point to point designs have both the DDR3 memory IC and the controller (CPU, FPGA, etc.) on the same PCB. The lack of connectors and shorter traces in point to point design allow some simplification of the DDR3 routing rules. I'm still finalizing my DDR3 rules, but I've found the Micron design guide for point to point designs (TN-41-13) to be very helpful.

Figures 1 thru 4 below show Micron's recommended address/control routing topologies. Since I'm only planning to use a single DRAM, the difference between fly-by and tree architectures is negligible. I settled on the topology on Figure 1 (tree architecture with series R) mostly because it doesn't require a VTT power rail and the signal quality should be better with the series R than without (Figure 2).

I've started routing and have hit some hurdles. I'll post some pictures of the route next time and talk about what I'm trying to fix.

Figure 1. Tree Architecture with series R and Vtt pull-up (from TN-41-13)

Figure 2. Tree Architecture with no R (from TN-41-13)

Figure 3. Tree Architecture with series R (from TN-41-13)

Figure 4. Fly-by Architecture with Vtt pull-up (from TN-41-13)