Wednesday, August 13, 2014

Impedance and PCB-Pool

I've been looking into low cost options for prototyping PCBs for some time now. I originally used OSH Park and I was pleased with their prices and build quality, but for more complicated designs I kept running across electrical errors even when I met their design guidelines (post). In my casting about for another low cost PCB prototyping house I ran across PCB-Pool. What excited me about PCB-Pool was that they offered both flying-lead electrical testing and free metal stencils. Hopefully this will avoid the problems that I had with my dense designs from OSH Park.

Kevin and I have been trying to address our biggest concerns with PCB-Pool: Can we really route a 0.8mm BGA and meet their design rules and can we rationally route impedance controlled designs using their PCB stack-up. Kevin spoke with an engineer at PCB-Pool and got a good answer for the first question: They said that we can route using slightly smaller traces than their rules allow and we can expect it to work (and the electrical testing will confirm it). I've been looking into impedances.

Figure 1. PCB Stackup from PCB-Pool Specifications

To calculate the impedance for traces on the top layer I used the MMTL Electromagnetic Simulator. Unfortunately PCB-Pool's stack-up isn't ideal for the 50 Ohm traces needed for PCI Express and DDR3. I would usually design a custom stack-up so that traces somewhere between 4 and 6 mils would have a characteristic impedance of 50 Ohms. PCB-Pool's thicker pre-preg layers means that 50 Ohm traces will need to be 14.4mils thick. With traces that wide we will have to neck them down to escape route from the ICs. Hopefully the neck-downs won't degrade the signal quality too much. As we test and simulate more I will post if I have any interesting results.

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