New address route

I finished connecting the DDR3 to the FPGA (thru the series resistors) using 0.125mm (4.92mil) traces. The route looks very clean and there is plenty of room left to tune the traces lengths. I'm going to do the initial route of the data lines next and then I'll start tuning. Figure 1 shows the new route with both routing layers shown at the same time. Figures 2 and 3 show the old, fat, route for reference.

This route was fast and I expect the data bytes to be just as quick.

Figure 1. New Top and Inner Layer DDR3 Route with Thin Traces

Figure 2. Top Layer DDR3 Route with Fat Traces.

Figure 3. Inner Layer DDR3 Route with Fat Traces.

The PCB layout shown in this post by Custom Embedded Solutions, LLC. is licensed under a Creative Commons Attribution 4.0 International License.