Fat, fat traces

As I mentioned in the last post, I decided to route the DDR3 memory using a series R tree architecture. My initial analysis showed that I needed to use very thick traces to get a 50 Ohm impedance using PCB-Pool's default stack-up. I didn't complete the route, but I got close enough that it looked possible to connect everything. Several problems became apparent:

• In Figure 1, the control traces on the lower left hand corner connecting the DDR3 IC and the series resistors had to fan out in a wide pattern to the left of the DDR3 IC. This makes the overall memory layout large given the size of the components. Since the control traces have to be length matched, the large trace distance difference between the traces connecting to the top versus the bottom resistors implies that the top traces will need a lot of tuning 'wiggles'.
• Normally the control nets (left side of the DDR3 IC in Figures 1 and 2) are routed vertically between the DDR3's fanout vias. The wide fanout that the large traces required will make re-use of this layout in designs with multiple DDR3 ICs unlikely
• The data bus routes on the right side of the DDR3 IC on the inner layer and the bottom layer (Figures 2 and 3) will be even more challenging to tune. I met my goal of routing a byte per layer, but the traces are so close that there is no tuning room left.

When I re-read Micron's design guide for point to point designs (TN-41-13) this morning, I realized that I overlooked a critical note on pages 15-16: "The tree with series R provides acceptable signal quality without having to provide VTT power when there is a mismatch between the driver and transmission line. The tree without series R option generally provides acceptable signal quality without having to provide VTT power when there is a minimal mismatch between the driver and transmission line".

My route was trying to both match the transmission line impedance (thick traces) and use series resistors. According to TN-41-13 this is overkill. I should pick one strategy or the other, not both. Since PCB-Pool's pricing is so attractive, I'm going to stick with the series resistors and use much smaller trace widths. I should be able to simulate the layout and validate if this approach will work.

Figure 1. Top Layer DDR3 Route

Figure 2. Inner Layer DDR3 Route.

Figure 3. Bottom Layer DDR3 Route.

The PCB layout shown in this post by Custom Embedded Solutions, LLC. is licensed under a Creative Commons Attribution 4.0 International License.